Abstract：
In this talk, two distinct topics will be covered. First, we will look at Noise-Shaping (NS) SAR ADCs, which have become popular recently thanks to their low-power
and high-resolution features. A brief summary and benchmark of different discrete-time (DT) NS-SAR implementations in literature is given. An open-loop duty-cycled residue amplifier is selected as a power-efficient solution to realize high residue gain in the loop filter. Then, a digital-predicted mismatch error shaping technique is added to improve the DAC linearity. The proposed DT NS-SAR ADC achieves 80 dB SNDR, 98 dB SFDR in a 31.25 kHz bandwidth while consuming 7.3 μW. In the second part of this presentation, we will look at a very low power temperature sensor. A duty-cycled resistive bridge is used as temperature sensor, and a dynamic SAR ADC as the readout system. By means of duty cycling and power gating, a low power consumption is achieved. Thanks to correlated double sampling and on-chip analog correction features for offset, gain, and distortion, the overall system achieves a resolution of 0.5K and an inaccuracy of ±0.7K, while consuming 2.98pJ/conversion and occupying only 0.0023mm2 in a 65nm CMOS process.
Biography：
Pieter Harpe received the M.Sc. and Ph.D. degrees from the Eindhoven University of Technology, The Netherlands. He spent several years as researcher at imec, The Netherlands, and joined Eindhoven University of Technology in 2011, where he is currently an Associate Professor on low-power mixed-signal circuits. Dr. Harpe is analog subcommittee chair for the ESSCIRC conference, TPC member for A-SSCC, and SSCS CONFedu program chair. He served as ISSCC ITPC member, SSCS Distinguished Lecturer, JSSC guest editor, and co-organizer for the AACD workshop. He is a Senior Member of the IEEE and recipient of the ISSCC 2015 Distinguished Technical Paper Award.